1. Field of the Invention
This invention relates to a three dimensionally structured latch and pass transistor which is useful, for example, in conjunction with field programmable gate arrays (FPGAs) and the like and, more specifically, for providing high density field reconfigurable programmable gate array architectures.
2. Brief Description of the Prior Art
Prior art field programmable gate arrays have generally been of two types. The first type of FPGA uses an anti-fuse as the pass element wherein two runs of metal which are normally separated and have an open circuit therebetween are short circuited to each other when so programmed by a metal run or interconnect therebetween. Such devices are one time programmable and cannot be reconfigured after initial programming.
A second type of FPGA uses a static random access memory (SRAM) based element and a pass transistor between the metal runs which is controlled by the SRAM or latch. The pass transistor is turned on when the programming as applied to the SRAM calls for short circuiting of the metal runs to each other. This type of FPGA is reconfigurable since the short circuit between the metal runs can be removed by reprogramming the SRAM to the opposite state, thereby turning off the pass transistor and providing an open circuit between the metal runs.
While the second type of FPGA as described hereinabove can properly provide the function for which it is designed, both the SRAM and the pass device have always been fabricated in bulk silicon. Accordingly, the FPGA has been two dimensional and therefore presented limitations on the density of elements that can be incorporated into the array for a given area.